ASIC design Jobs

Python C++Linux Machine learning ASIC design RTL design FPGA SystemVerilog Problem solving

Ability to describe hardware designs at a high level, low level, or anywhere in between Brilliant design, optimization, debugging and problem solving skills…

Senior Design Engineer, ASIC

Waymo

Mountain View, CA, USA8d ago

Senior

Python C++Machine learning ASIC design RTL design Physical design Formal verification SystemVerilog Verilog

Master's or PhD degree in Engineering Experience leading or managing engineering teams Experience with the full digital design verification cycle -- from spec…

Silicon DFT Architect

Waymo

Mountain View, CA, USA8d ago

Lead

Python ASIC design RTL design Physical design

10+ years of experience on DFT/ATPG/Silicon Test in advanced silicon nodes with a minimum of 2 tapeouts Experience owning full chip DFT architecture. Be able…

Senior Firmware Engineer I (FPGA)

Rocket Lab Corporation

Python MATLAB Security ASIC design RTL design FPGA Verilog VHDL

Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus Regularly…

Senior Firmware Engineer II/Principal Engineer (FPGA)

Rocket Lab Corporation

Python MATLAB Security ASIC design RTL design FPGA Verilog VHDL

Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus. Regularly…

Hardware Design Engineer - 2026 Grads

Hudson River Trading

Chicago, Illinois, United States; New York, NY, United States8d ago

Python C++Linux Machine learning ASIC design RTL design FPGA SystemVerilog Problem solving

Currently pursuing a Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related discipline, with eligibility for…

Design Verification (DV) Engineer

Hudson River Trading

Austin, TX, United States; Chicago, Illinois, United States; London, United Kingdom; New York, NY, United States8d ago

Python C++CI/CD Linux Machine learning ASIC design RTL design FPGA SystemVerilog Verilog

Superb debug and analytical skills Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional…

AI Researcher

Hudson River Trading

London, United Kingdom; New York, NY, United States; Seattle, Washington, United States8d ago

C++Deep learning PyTorch LLM ASIC design FPGA Large language models

Must have two or more years work experience in deep learning research, for any domain: robotics, biology, chemistry, physics, audio, video, etc. Experience…

Hardware Machine Learning Engineer

IMC

Chicago, United States; New York, United States8d ago

Python ASIC design RTL design Cadence Physical design Verilog Problem solving Documentation

Python C++Machine learning Deep learning ASIC design RTL design FPGA SystemVerilog Verilog VHDL+3

Extensive experience with FPGA or ASIC technologies, including proficiency in either VHDL, Verilog, or SystemVerilog Solid understanding of digital design…

Senior Firmware Engineer II/Principal (TS/SCI)

Rocket Lab Corporation

Python MATLAB Security ASIC design RTL design FPGA Verilog VHDL

Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus. Regularly…

Sr. Digital Implementation Engineer

AlifSemi

Significant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing Closure Familiarity with DFT (Tessent) and back-end (Cadence)…

Senior CAD Engineer

Aeva

Python JavaScript Shell scripting CSS Kubernetes CI/CD Linux Git ASIC design RTL design+3

B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years…

FPGA Engineer

Jane Street

London, England, United Kingdom8d ago

Austin, Texas, United States; Fremont, California, United States8d ago

Python Java C++OCaml Haskell ASIC design RTL design FPGA

Have practical experience in RTL design and verification Experienced with either Vivado or Quartus in the following areas: High-speed FPGA design…

Senior Firmware Engineer II/Principal (TS/SCI)

Rocket Lab Corporation

Python MATLAB Security ASIC design RTL design FPGA Verilog VHDL

Specific vision abilities required by this job include close vision, distance vision, peripheral vision, depth perception, and the ability to focus. Regularly…

Physical Design and Verification Engineer

Neuralink

Python Shell scripting Linux ASIC design RTL design Physical design Bazel

Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Minimum 5 years of…

ASIC Engineer

Jane Street

London, England, United Kingdom9d ago

Python Java C++OCaml Haskell ASIC design RTL design FPGA Cadence Physical design

Have practical experience in RTL design and verification Experienced in ASIC design using either Synposys or Cadence flows, including at least one of the…

FPGA Engineer

Jane Street

New York, New York, United States8d ago

New York, New York, United States8d ago

Python Java C++OCaml Haskell ASIC design RTL design FPGA

Have practical experience in RTL design and verification Experienced with either Vivado or Quartus in the following areas: High-speed FPGA design…

ASIC Engineer

Jane Street